1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor memory device. More particularly, the present invention relates to a nonvolatile memory using an insulating film as a charge storage layer.
2. Description of the Related Art
As a structure of a memory cell transistor in a nonvolatile memory, a metal oxide nitride oxide semiconductor (MONOS) type structure has been conventionally known. The MONOS type structure is a structure having: a charge storage layer (e.g., an insulating film) formed on a silicon substrate through an insulating film; an insulating film which is formed on the charge storage layer and has a higher dielectric constant than the charge storage layer (which will be referred to as a block layer hereinafter); and a control gate electrode formed on the block layer (see, e.g., “Charge Trapping Memory Cell of TANOS (Si-Oxide-SiN—Al2O3—TaN) Structure Compatible to Conventional NAND Flash Memory,” IEEE NVSMW 2006. 21st Volume, Issue 2006 pp. 54-55).
The nonvolatile memory requires peripheral transistors constituting, e.g., a power supply generation circuit or a decoder circuit besides the memory cell transistors. An impurity that is implanted into the silicon substrate and energy that is used to implant the impurity vary depending on the types of these transistors. Therefore, the memory cell transistor is protected by, e.g., a photoresist when, e.g., forming the peripheral transistors. Therefore, the memory cell transistor is exposed to wet etching that is performed to remove, e.g., a photoresist more than once.
During this wet etching, not only the photoresist but also the block layer of the memory cell transistor may be simultaneously etched in some cases. As a result, the memory cell transistor having the etched block layer has a problem of degradation in characteristics of the nonvolatile memory, e.g., a reduction in a data writing speed or erasing speed.